1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise gate electrode structures including a high-k gate dielectric.
2. Description of the Related Art
Advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, include a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of integrated circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the scaling of the channel length, and associated therewith the reduction of channel resistivity, which in turn causes an increase of gate resistivity due to the reduced dimensions, has been a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has been preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density to provide the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, usage of high speed transistor elements having an extremely thin gate dielectric may be restricted to high speed signal paths, whereas transistor elements with a thicker gate dielectric may be used for less critical circuit portions, such as storage transistor elements and the like, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for many types of circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
As is well known, the work function of the gate dielectric material may significantly affect the finally obtained threshold voltage of field effect transistors, which is presently accomplished by appropriately doping the polysilicon material, which may be used in combination with a silicon oxide-based material in conventional gate electrode structures. Upon introducing a high-k dielectric material, the adjustment of an appropriate work function may require the incorporation of appropriate metal species into the gate dielectric material, for instance in the form of lanthanum, aluminum and the like, in order to obtain appropriate work functions and thus threshold voltages for P-channel transistors and N-channel transistors. Moreover, the sensitive high-k dielectric material may have to be protected during the processing, while a contact with well-established materials, such as silicon and the like, may also be considered disadvantageous since the Fermi level may be significantly affected upon contacting a high-k dielectric material, such as hafnium oxide, with a polysilicon material. Consequently, a metal-containing cap material may typically be provided on the high-k dielectric material when provided in an early manufacturing stage. Additionally, the metal-containing material may provide superior conductivity and may also avoid any depletion zone, which may be observed in polysilicon gate electrode structures. Consequently, a plurality of additional process steps and material systems are introduced in well-established CMOS process techniques in order to form gate electrode structures including a high-k dielectric material in combination with a metal-containing electrode material. In other approaches, replacement gate approaches may be applied in which essentially gate electrode structures may be provided as placeholder material systems, wherein, after finishing the basic transistor configurations, the gate electrode structures may be replaced by at least an appropriate metal-containing electrode material, possibly in combination with a high-k dielectric material, thereby requiring complex process sequences for removing the initial gate material, such as polysilicon, and forming appropriate metal species, wherein appropriate work function values also have to be adjusted by incorporating corresponding work function adjusting species, as discussed above.
In addition to enhancing performance of gate electrode structures by incorporating a high-k dielectric material in sophisticated semiconductor devices, frequently, transistor elements of different characteristics, for instance of different leakage behavior, have to be provided, thereby requiring a gate dielectric material of different material composition and/or of different thickness. In some conventional approaches, the high-k dielectric material in combination with any work function adjusting species are provided in an early manufacturing stage, wherein a different thickness of the gate dielectric material may also be provided in different device regions in order to provide different transistor types, or any other circuit elements, such as polysilicon resistors and the like. It turns out, however, that the conventional process strategy for providing gate electrode structures with differently composed gate dielectrics may result in significant threshold voltage variations, as will be described in more detail with reference to FIGS. 1a-1g. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 which comprises a substrate 101 and a semiconductor layer 102 formed above the substrate 101. The semiconductor layer 102 is typically provided in the form of a silicon material, as explained above. Moreover, a first semiconductor region or active region 102A and a second semiconductor region or active region 102B are provided in the semiconductor layer 102. The active regions 102A, 102B are to be understood as semiconductor regions in and above which transistor elements are to be formed on the basis of gate electrode structures including a high-k dielectric material. In the example shown, it may be assumed that a gate electrode structure of reduced gate dielectric thickness is to be formed on the semiconductor region 102A, while a gate electrode structure having a gate dielectric material of increased thickness is to be formed on the semiconductor region 102B. Furthermore, in the manufacturing stage shown, a gate dielectric material 151 is selectively formed on the active region 102B and is comprised of silicon dioxide with a specific thickness, for instance with a thickness of several nanometers, depending on the device requirements or any transistors to be formed in and above the semiconductor region 102B.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of well-established process techniques including processes for forming an isolation structure (not shown) in order to laterally define the lateral size and position of the active regions 102A, 102B. Moreover, a basic dopant concentration may be established in the regions 102A, 102B corresponding to the conductivity type of the transistors to be formed in the respective active region. As previously explained, since a significant threshold voltage variability may exist between transistor elements of reduced thickness of the gate dielectric material relative to transistors with an increased thickness, in some cases, a corresponding countermeasure may be applied by appropriately providing a well dopant profile in the active region 102B in order to obtain the desired threshold voltage. For example, a certain degree of counter-doping may be introduced into the active region 102B, which, on the other hand, may reduce the overall charge carrier mobility in a channel region of a corresponding transistor still to be formed. Next, the dielectric layer 151 may be formed, for instance, by well-established deposition techniques, in order to obtain a silicon oxide-based material having the desired thickness and material composition. Thereafter, an etch mask 103, such as a resist mask and the like, may be provided on the basis of lithography techniques so as to expose a portion of the layer 151 above the active region 102A, while covering the material 151 above the active region 102B. Thereafter, an appropriate etch process 104 may be performed, for instance, on the basis of wet chemical etch recipes, plasma assisted etch recipes and the like, in order to remove the exposed portion of the layer 151 selectively to the underlying silicon material in the region 102A.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing phase in which the etch mask 103 is removed and the device 100 is exposed to a cleaning ambient 105 in order to remove contaminants and also to re-grow a thin dielectric base layer 152 on the semiconductor region 102A. For this purpose, a plurality of well-established process techniques are available in order to obtain a silicon dioxide material on the basis of a well-controllable growth process.
FIG. 1c schematically illustrates the semiconductor device 100 when exposed to a deposition ambient 106 in which a high-k dielectric material, such as hafnium oxide, is deposited above the active regions 102A, 102B, thereby forming a high-k dielectric layer 153. Thus, the layers 152 and 153 in combination may represent the gate dielectric material of a transistor to be formed in and above the semiconductor region 102A, thereby providing the required characteristics for high performance transistors, while the layer 153 in combination with the “thick” silicon dioxide material 151 represents the dielectric material for transistors and other circuit elements in which a superior performance with respect to reduced leakage currents and the like is required. It should be appreciated that the deposition process 106 may be performed on the basis of any appropriate deposition recipe, for instance, by chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like. For example, a thickness of the high-k dielectric layer 153 may be in the range of one to several nanometers, depending on the overall requirements in view of capacitive coupling, leakage currents and the like.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, a titanium nitride material 107 is formed on the high-k dielectric material 153, thereby providing reliable enclosure of the sensitive material 153 during the further processing of the device 100. Titanium nitride has proven to be a viable material in combination with sophisticated high-k metal gate electrode structures in view of confining sensitive high-k materials acting as an etch stop material, providing superior conductivity, for instance, compared to doped polysilicon material, and the like. Typically, the titanium nitride layer 107 may be deposited by any appropriate deposition technique with a thickness of approximately one nanometer to several nanometers. Moreover, a further material layer, such as a metal layer 154, with a thickness of several Angstrom, may be formed on the titanium nitride layer 107 and may be comprised of an appropriate metal species in order to adjust the work function and thus the threshold of transistor elements to be formed in the active regions 102A, 102B. As previously explained, the layer 154 may be provided with different material characteristics for transistors of different conductivity type, such as P-channel transistors and N-channel transistors, in order to adjust an appropriate work function for each transistor type. For convenience, the material 154 in the active regions 102A, 102B may be provided for one type of transistor, such as an N-channel transistor or a P-channel transistor, and may thus include any appropriate species, such as lanthanum for an N-channel transistor or aluminum for a P-channel transistor, and the like. In other device regions in which the material 154 may be inappropriate for adjusting the desired threshold voltage, any portions of these materials may be selectively removed by any appropriate lithography and etch technique and subsequently a further material may be deposited, possibly in combination with an additional titanium nitride layer, if required.
Next, the semiconductor device 100 may be annealed at temperatures of approximately 700-900° C. in order to initiate the diffusion of the species in the layer 154 through the titanium nitride material 107 into the high-k dielectric material 153 so as to finally form the work function adjusting species at an interface 153S formed between the materials 152 and 153 above the semiconductor region 102A and formed by the materials 151 and 153 above the semiconductor region 102B. If required, the process 108 may include any further anneal step for stabilizing the metal species at the interface 153S, which may include the incorporation of a further species, such as nitrogen and the like, if considered appropriate. Thereafter, any residue of the layer 154 is removed and the titanium nitride material 107 may also be removed in order to provide superior conditions during the subsequent processing of the device 100, for instance in terms of patterning a gate layer stack, since the previously treated titanium nitride material 107 may otherwise result in pattern-related irregularities during the complex gate patterning process.
FIG. 1e schematically illustrates the semiconductor device 100 with the exposed high-k dielectric material 153, which may now comprise fixed charges 153A, 153B in the form of the previously diffused metal species in order to obtain a desired work function for the transistors to be formed in and above the active regions 102A, 102B in the subsequent processing. As previously explained, upon forming transistor elements on the basis of the layer systems 152 and 153 above the region 102A and the layers 151 and 153 above the region 102B, a significant difference in threshold voltage may be observed, wherein the reason for this variability is not yet understood. Without intending to restrict the present application to the following explanation, it is believed that the different position of the fixed charges 153A compared to the fixed charges 153B with respect to the silicon material may strongly affect the resulting threshold voltage, which may require significant modifications in order to re-adjust the difference in threshold voltage.
FIG. 1f schematically illustrates the semiconductor device 100 with a further titanium nitride layer 155 formed on the high-k dielectric layer 153 in order to confine the material 153 and stabilize the work function adjusting species contained therein. For this purpose, any appropriate deposition technique may be applied, as previously discussed. Based on the material system shown in FIG. 1f, the further processing may be continued by depositing a silicon material, possibly in combination with additional cap materials and the like, as may be required for the further processing of the device 100. For instance, any hard mask materials, for instance in the form of amorphous carbon and the like, in addition to cap materials in the form of silicon nitride and the like, may be deposited based on well-established process techniques. Thereafter, the resulting material stack is patterned by applying sophisticated lithography techniques for forming an appropriate hard mask followed by anisotropic etch techniques for etching through the silicon material, through the titanium nitride material 155, the high-k material 153 and the dielectric materials 152 and 151, respectively.
FIG. 1g schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a gate electrode structure 150A is formed above the active region 102A and comprises the layers 152, 153 and 155 in combination with a polysilicon material 156. Moreover, a sidewall spacer structure 157 is formed on sidewalls of the materials 152, 153, 155 and 156. Similarly, a gate electrode structure 150B is formed on the active region 102B and comprises the polysilicon material 156 and the layers 155 and 153, wherein the silicon dioxide material 151 may provide the increased thickness of the combined gate dielectric material. Furthermore, drain and source regions 161 are formed in the active regions 102A, 102B. The drain and source regions 161 may be formed on the basis of well-established process techniques, such as ion implantation and the like, wherein the spacer structure 157 may be used as an implantation mask during some of the required implantation steps. As previously indicated, the transistors 160A, 160B may have a different threshold voltage for a given configuration of the drain and source regions 161 and the channel region 162, which may require additional process steps for re-adjusting the threshold voltage of at least one of the transistors 160A, 160B. For instance, as previously explained, a counter-doping may be introduced into the active region 102B which, however, may result in a deteriorated charge carrier mobility in the channel region 162. In other cases, at least for P-channel transistors, a band gap offset obtained by providing a silicon/germanium alloy on the basic silicon material may be re-adjusted, for instance, by increasing the thickness of a corresponding channel semiconductor alloy and/or by increasing a germanium concentration, possibly in combination with a modified well doping in the active region 102A, which may introduce additional defects during the epitaxial growth of a corresponding semiconductor material.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.